(a) Field of the Invention
The present invention relates to a semiconductor device having a protective circuit, and more particularly to a structure of a protective transistor capable of protecting the internal circuit of the semiconductor device against an electrostatic breakdown.
(b) Description of the Related Art
In general, when electrostatic charge enters a semiconductor device during the course of a fabrication or inspection process, or during a stage of mounting the semiconductor device onto electronic equipment, the internal circuit of the semiconductor device is prone to breaking. Therefore, a protective transistor is generally provided at an input/output port of a semiconductor device through which the internal circuit is connected to an external circuit.
FIGS. 1A and 1B show two of a plurality of input/output circuit sections of a typical semiconductor device. These input/output circuit sections are provided at peripheral portions of a chip of the semiconductor device so as to surround the internal circuit. Each of the input/output circuit sections is composed of paired nMOSFETs 31 and pMOSFETs 32. As shown in FIGS. 1A and 1B, by means of interconnects overlying the substrate, the input/output circuit section is fabricated selectively as a protective circuit or an output buffer. Alternatively, a portion of the input/output circuit section is fabricated as a protective circuit and the remaining portion is formed as an output buffer. The structure of such a transistor will be described with reference to the nMOSFET 31. In the present example, each nMOSFET 31 includes four protective transistors. The drain region 14n are connected to a pair of gate electrodes 15n in common. Similarly, the source regions 16n formed are connected to a pair of gate electrodes 15n in common. A via hole 13 provides connection between an overlying interconnect layer and an underlying drain region 14n or source region 16n. Each guard ring 18n is formed to surround the drain regions 14n and the source regions 16n and is connected to the ground line GND (in the case of nMOSFET 31). The guard ring 18n surrounding the transistors fixes the potential of the well or the substrate. In the case of nMOSFET 31, the drain regions 14n and the source regions 16n are implemented by an N+ diffused layer, the guard ring 18n is implemented by a P+ diffused layer, and the well 11n is of a P-conductivity type. By contrast, in the case of pMOSFET 32, the drain regions 14p and the source regions 16p are formed of a P+ diffused layer, the guard ring 18p is formed of an N+ diffused layer, and the well 11p is of an N-conductivity type. The guard ring 18p is connected to a power supply line VDD.
FIG. 1A is a top plan view of the input/output circuit section in the case of an input protective circuit, and FIG. 2A is an equivalent circuit diagram of the input/output circuit section of FIG. 1A. The drain regions 14n of the nMOSFET 31 and the drain regions 14p of the pMOSFET 32 are connected together, via an overlying interconnect 14a, to a pad 22 and an unillustrated input buffer of the internal circuit. The source regions 16n of the Cap nMOSFET 31 are connected, via the via holes 13, to the gate electrodes 15n as well as to the ground line GND. The source regions 16p of the pMOSFET 32 are connected, via the via holes 13, to the gate electrodes 15p as well as to the power supply line VDD. Through these connections, the input/output circuit section functions as an input protective circuit.
FIG. 1B is a top plan view of the input/output circuit section in the case of an output buffer, and FIG. 2B is an equivalent circuit diagram of the input/output circuit section of FIG. 1B. The drain regions 14n of the nMOSFET 31 and the drain regions 14p of the pMOSFET 32 are connected to another pad 22 via another interconnect 14a. The gate electrodes 15n and 15p are connected to an output of an unillustrated output pre-buffer of the internal circuit. When the output pre-buffer has a pair of complementary output lines, the gate electrodes 15n and 15p are connected to the output pre-buffer via a pair of signal lines. When the output pre-buffer has a single output, the gate electrodes 15n and 15p are connected to the output pre-buffer via a single signal line (not illustrated). The source regions 16n of the nMOSFET 31 are connected to the ground line GND via the via holes 13, and the source regions 16p of the pMOSFET 32 are connected to the power supply line VDD via the via holes 13. Through these connections, the input/output circuit section functions as an inverter and as a protective circuit.
FIG. 2C is an equivalent circuit diagram of an input/output circuit section, a part of which is formed as an input protective circuit, and the remaining portion of which is formed as an output buffer. In this case, among four transistors of each of the pMOSFET 32 and the nMOSFET 31, two transistors are used in order to form the input protective circuit, and the remaining transistors are used in order to form the output buffer. The connections for formation of the input protective circuit and the connections for formation of the output buffer are performed similarly to the case as described above. That is, the drain regions 14n of the nMOSFET 31 and the drain regions 14p of the pMOSFET 32 are connected together to the pad 22 via the interconnection layer 14a. The source regions 16n of the nMOSFET 31 constituting the input protective circuit are connected, via the via holes 13, to the gate electrodes 15n thereof as well as to the ground line GND. The source regions 16p of the pMOSFET 32 are connected, via the via holes 13, to the gate electrodes 15p thereof as well as to the power supply line VDD. The gate electrodes 15n and 15p of the transistors constituting the output buffer are connected to an unillustrated output pre-buffer of the internal circuit. The source regions 16n of the nMOSFET 31 are connected to the ground line GND via the via holes 13, and the source regions 16p of the pMOSFET 32 are connected to the power supply line VDD via the via holes 13. Through these connections, the input/output circuit section functions as an input protective circuit and as an output buffer.
Next, the operation of the input protective circuit formed by the input/output circuit section will be described with reference to FIGS. 3A and 3B. FIG. 3A is a cross section of the guard ring 18n of the nMOSFET 31 and a protective transistor adjacent thereto. FIG. 3B is a graph showing the input/output characteristics of the protective transistor. In FIG. 3A, since the drain 14n and the source 16n are formed of an N+ diffused layer, and a portion of the P-well 11 located beneath the gate 15n is of a P-conductivity type, an NPN parasitic transistor 12 is formed beneath the gate 15n. Specifically, the drain 14n corresponds to the collector 14c, the P-well 11 corresponds to the base 11c, and the source 16n corresponds to the emitter 16c of the parasitic transistor 12. The collector 14c is connected to the pad 22, and the emitter 16c is connected to the ground together with the guard ring 18n. A parasitic resistor 17 is formed between the base 11c and the guard ring 18n. In an ordinary state, since no voltage is applied to the base 11c, the parasitic transistor 12 is in an off state.
Next, the principle of the protective transistor will be described with reference to FIG. 3B. The abscissa represents the emitter-to-collector voltage (source-to-drain voltage), and the ordinate represents the collector current. Assuming that, due to electrostatic charge, positive surge voltage enters from the pad 22, a strong electric field is generated between the collector 14c and the emitter 16c, with the result that breakdown starts in the drain region 14n in the vicinity of the gate 15n (at BVDS {circle around (3)} in FIG. 3B). Due to this breakdown, a small breakdown current flows from the pad 22 into the P-well 11 and then flows to the ground via the parasitic resistor 17 and the guard ring 18n through a path {circle around (1)} in FIG. 3A). When the small breakdown current flows through the parasitic resistor 17, a voltage is generated across the parasitic resistor 17 with a resultant increase in the potential of the base 11c. When the potential of the base 11c relative to the emitter 16c exceeds 0.6 to 0.7 volts (i.e., the threshold voltage VBE of the parasitic transistor), the parasitic transistor 12 turns on, resulting in that current starts to flow from the collector 14c to the emitter 16c through a path {circle around (2)} in FIG. 3A). The collector voltage at this stage will be referred to as an initial breakdown voltage V1 and the collector current at this stage will be referred to as a collector current I1 (point {circle around (4)} in FIG. 3B). When the parasitic transistor 12 turns on, the emitter-to-collector voltage decreases abruptly to a snap-back voltage Vsnp that is determined at point {circle around (5)} in FIG. 3B in accordance with the performance of the parasitic transistor 12.
When the current due to the ESD surge increases further, the current starts to flow to ground via the parasitic transistor 12 and the parasitic resistor 17 through paths {circle around (1)} and {circle around (2)} in FIG. 3A. However, due to the internal resistance of the parasitic transistor 12, the emitter-to-collector voltage increases with the collector current as shown as a snap-back region in FIG. 3B. When the emitter-to-collector voltage exceeds the withstand voltage of the parasitic transistor 12, the parasitic transistor 12 is destroyed at the state {circle around (6)} shown in FIG. 3B. The emitter-to-collector voltage at the time of breakage of the parasitic transistor 12 is represented by Vmax, and the collector current at the time of breakage is represented by Imax in FIG. 3B.
Although the pMOSFET 32 operates similarly to the case of nMOSFET 31, the operation of the pMOSFET 32 differs from that of the nMOSFET 31 in that the pMOSFET 32 provides protection against negative surge voltage, because a PNP parasitic transistor is formed in the pMOSFET 32. In this way, even when an ESD surge on the order of tens of thousands volts is applied to the pad 22, the voltage of the drain 14n can-be suppressed to as low as a few tens of volts by the protective circuit including the nMOSFET 31 and the pMOSFET 32. Accordingly, an extreme high voltage due to ESD surge is not transmitted to the internal circuit, thereby preventing break down of the internal circuit.
In the protective circuit, the initial breakdown voltage V1 varies depending on the resistance of the parasitic resistor 17. In order to protect the internal circuit, the voltage V1 is preferably decreased to a possible extent. However, if the parasitic transistor 12 operates in response to ordinary signals, the internal circuit will fail to function. Therefore, the initial breakdown voltage V1 must be greater than several times the voltage of ordinary signals. In order to secure a desired initial breakdown voltage V1, the resistance of the parasitic resistor 17 of the P-well 11 must be set to a specific value. The impurity concentration of the P-well 11 is determined in accordance with the performance of transistors that constitute the internal circuit and other factors, and therefore, the resistance of the parasitic resistor 17 can be determined through change of the impurity concentration of the P-well 11. If the impurity concentration of the P-well 11 is to change, separate processes for forming different wells must be provided for the internal circuit and the input/output circuit section in order to change the impurity concentration of the P-well 11. This increases the number of processes, with a resultant increase in the cost of the semiconductor device. Therefore, this method is not preferred.
In order to set the resistance of the parasitic resistor 17 at the specific value, the distance 20 between the source 14n and the guard ring 18n may be set to a desired value. Incidentally, in response to demands for reduction in cost and increase in operational speed of semiconductor devices, transistor elements that constitute an internal circuit have been progressively miniaturized year after year. In order to reduce the size of a semiconductor device, the impurity concentration of the substrate must be increased in accordance with the scaling-down rule. Since the resistivity of the substrate decreases as the impurity concentration increases, the distance between the guard ring and the source should be increased for a larger resistance. In an exemplified case where the impurity concentration of the substrate is 2.0xc3x971017 cmxe2x88x923, the distance between the guard ring and the source should be set at 10 xcexcm. However, this relatively large distance increases the area occupied by the protective transistor, hindering efforts to increase the degree of integration.
In view of the foregoing, an object of the present invention is to provide a structure of a protective transistor suitable for miniaturized semiconductor devices.
The present invention provides, in an embodiment thereof, a semiconductor device including a semiconductor substrate having a substrate region of a first conductivity type or a second conductivity type opposite to the first conductivity type, a well region of the first conductivity type formed on a surface region of the semiconductor substrate and having a first impurity concentration, a guard ring of the first conductivity type disposed on a surface region of the semiconductor substrate within the well region, a MOS transistor having source/drain regions of the second conductivity type and surrounded by the well region, and a diffused region disposed between the source/drain regions of the MOS transistor and the guard ring, the diffused region being of the first conductivity type having a second impurity concentration lower than the first concentration or of the second conductivity.
In accordance with the embodiment of the semiconductor device of the present invention as described above, since the substrate region of a first or second conductive type is provided between the source of a protective transistor and the guard ring, the parasitic resistance of the parasitic bipolar transistor can be increased, resulting in that the distance between the source and the guard ring need not be large, and thus, a small chip size for the semiconductor device can be obtained.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.